1. Field of the Invention
Generally, the subject matter disclosed herein relates to the field of manufacturing integrated circuits, and, more particularly, to chemical mechanical polishing (CMP) processes used for planarizing process layers, such as metallization structures, when removing the excess metal using a polishing process.
2. Description of the Related Art
Typically, the fabrication of modern integrated circuits requires a large number of individual process steps, wherein a typical process sequence involves the deposition of conductive, semiconductive or insulating layers on an appropriate substrate. After deposition of the corresponding layer, device features are produced by patterning the corresponding layer with well-known means, such as photolithography and etching. As a consequence, by patterning a deposited layer, a certain topography will be created that also affects deposition and patterning of subsequent layers. Since sophisticated integrated circuits require the formation of a plurality of stacked layers, it has become standard practice to periodically planarize the surface of the substrate to provide well-defined conditions for deposition and patterning of subsequent material layers. This holds true especially for so-called metallization layers in which metal interconnects are formed to electrically connect the individual device features, such as transistors, capacitors, resistors and the like, thereby establishing the functionality required by the circuit design.
In this respect, CMP has become a widely used process technique for reducing “imperfections” in the substrate topography caused by preceding processes in order to establish enhanced conditions for a subsequent process, such as photolithography and the like. The polishing process itself causes mechanical damage to the polished surface, however, in an extremely low range, i.e., at an atomic level, depending on the process conditions. CMP processes also have a plurality of side effects that have to be addressed so as to be applicable to processes required for forming sophisticated semiconductor devices.
For example, recently, the so-called damascene or inlaid technique has become a preferred method of forming metallization layers, wherein a dielectric layer is deposited and patterned to receive trenches and vias that are subsequently filled with an appropriate metal, such as aluminum, copper, copper alloys, silver, tungsten and the like. Since the process of providing the metal may be performed as a “blanket” deposition process based on, for instance, electrochemical deposition techniques, the respective pattern of the dielectric material may require a significant over-deposition in order to reliably fill narrow openings and wide regions or trenches in a common deposition process. The excess metal is then removed and the resulting surface is planarized by performing a process sequence comprising one or more mechanical polishing processes, which also include a chemical component. Chemical mechanical polishing (CMP), or generally planarization, has proven to be a reliable technique to remove the excess metal and planarize the resulting surface so as to leave behind metal trenches and vias that are substantially electrically insulated from each other as required by the corresponding circuit layout. Chemical mechanical polishing typically requires the substrate to be attached to a carrier, a so-called polishing head, such that the substrate surface to be planarized is exposed and may be placed against a polishing pad. The polishing head and polishing pad are moved relative to each other usually by individually moving the polishing head and the polishing pad. Typically, the head and pad are rotated against each other while the relative motion is controlled to locally achieve a target material removal rate for a given chemical reaction rate that is substantially determined by the composition of the slurry and the characteristics of the material(s) to be removed.
One problem involved in the chemical mechanical polishing of substrates is the very different removal rates of differing materials, such as of a metal and a dielectric material, from which the excess metal has to be removed. For instance, at a polishing state where the dielectric material and the metal are simultaneously treated, i.e., after the major portion of the metal has already been removed, the removal rate for the metal exceeds the removal rate for the dielectric material. This may be desirable, to a certain degree, because all metal is reliably ablated from all insulating surfaces, thereby insuring the required electrical insulation. On the other hand, significant metal removal from trenches and vias may result in a trench or via that exhibits an increased electrical resistance due to the reduced cross-sectional area. Moreover, the local removal rate may significantly depend on the local structure, i.e., on the local pattern density of the device features in a specific die area, which may result in a locally varying degree of erosion of the dielectric material in a final state of the polishing process. In order to more clearly demonstrate a typical CMP process in the context of a damascene process, reference is made to FIGS. 1a-1f. 
FIGS. 1a-1c schematically show cross-sectional views of a semiconductor structure 150 at various stages in fabricating a metallization layer according to a typical damascene process sequence.
In FIG. 1a, the semiconductor structure 150 comprises a substrate 151 bearing circuit features (not shown) and an insulating cap layer on which metal lines are to be formed. A patterned dielectric layer 152 is formed over the substrate 151 and includes openings, for example in the form of narrow trenches 153 and wide trenches 154. The dielectric layer 152 may also comprise closely-spaced openings 159. The openings for the trenches 153, 159 and 154 are patterned in conformity with design rules to establish metal lines exhibiting the required electrical characteristics in terms of functionality and conductivity. The openings 153, 154 and 159 may represent device regions of different pattern density, i.e., the number of device features, such as metal lines to be formed in the openings 153, 154, 159, per unit area of the regions substantially defined by the respective openings 153, 154, 159, respectively, is different. For example, the opening 154, representing a wide trench, may be considered as a region of reduced pattern density compared to a region accommodating the trenches 159. The deposition of the dielectric material 152 as well as the patterning of the trenches 153, 159 and 154 is carried out by well-known deposition, etching and photolithography techniques.
FIG. 1b schematically depicts the semiconductor structure 150 after deposition of a metal layer 155, for example a copper layer, when sophisticated integrated circuits are considered. As is evident from FIG. 1b, the topography of the metal layer 155 will be affected by the underlying pattern of the dielectric layer 152. The metal layer 155 may be deposited by chemical vapor deposition, sputter deposition or, as usually preferred with copper, by electroplating with a preceding sputter deposition of a corresponding copper seed layer. Although the precise shape of the surface profile of the metal layer 155 may depend on the deposition technique used, in principle, a surface shape will be obtained as shown in FIG. 1b. 
Subsequently, the semiconductor structure 150 will be subjected to the chemical mechanical polishing in which, as previously mentioned, the slurry and polishing pad are selected to efficiently remove the excess metal in the metal layer 155. During the chemical mechanical polishing, the excess metal is removed and, finally, surface portions 158 of the dielectric material 152 will be increasingly exposed, wherein it is necessary to continue the polishing operation for a certain over-polish time to ensure clearance of the metal from all insulating surfaces in order to avoid any electrical shorts or leakage paths between adjacent metal lines. As previously mentioned, the removal rate of the dielectric material and the metal may differ significantly from each other so that, upon over-polishing the semiconductor structure 150, the copper in the trenches 153, 159 and 154 will be recessed.
FIG. 1c schematically shows a typical result of chemical mechanical polishing of the structure shown in FIG. 1b. As is evident from FIG. 1c, during over-polishing the semiconductor structure 150, different materials are simultaneously polished with different removal rates. The removal rate is also dependent to some degree on the underlying pattern. For instance, the recessing of the metal lines during the over-polish time, which is also referred to as dishing, as well as the removal of the dielectric material, also referred to as erosion, is significantly affected by the type of pattern to be polished. In FIG. 1c, dishing and erosion at the wide trenches 154, as indicated by 157 and 156, respectively, are relatively moderate, whereas, at the narrow lines 153, dishing 157 and erosion 156 are significantly increased. For obtaining a required electrical conductivity, circuit designers have to take into consideration a certain degree of dishing and erosion, which may not be compatible with sophisticated devices.
Therefore, complex control strategies are typically used in advanced CMP tools in order to generate in situ measurement data for estimating an appropriate end point of the polishing process and/or control the uniformity of the polishing process. For example, a measurement signal indicative of the average layer may be monitored in order to determine the average removal rate during the process and/or to identify an appropriate point in time for terminating the process. To this end, optical measurement techniques, such as spectroscopic ellipsometry or other reflectivity measurement techniques, may be used. Since the optical probing of the substrate surface is difficult, due to the nature of the polishing process, significant efforts have been made to provide appropriate CMP tools comprising optical measurement capabilities. For this purpose, appropriately configured polishing pads and platens have been developed that allow optical access to the substrate surface during polishing. This may be accomplished by providing respective transparent windows in the pad. Respective optical measurement data may, therefore, be obtained for a plurality of dielectric materials and very thin metal layers during polishing, thereby enabling efficient control and endpoint detection strategies.
FIG. 1d schematically illustrates a top view of a CMP tool 100 comprising a frame 110 configured to accommodate a polishing platen 120, a polishing head 130 and a pad conditioner 160, as well as any respective mechanical, electrical and other components for operating the components 120, 130 and 160. It should be appreciated that the platen 120 is rotatably supported by appropriate drive assemblies (not shown) that are configured to provide a controllable rotation of the platen 120 in accordance with process parameters. Similarly, the polishing head 130 is configured, in combination with suitable mechanical, electrical, hydraulic, pneumatic and other components, to receive a substrate, such as the semiconductor substrate 151, and to rotate the substrate relative to the polishing platen 120 in accordance with the specified process parameters, wherein a specific downforce may be applied to the substrate for obtaining the desired interaction with a corresponding polishing pad (not shown in FIG. 1d), in combination with a suitable slurry substance, such as a chemical component and the like. Similarly, the pad conditioner 160 is connected to an appropriate drive assembly in order to provide the desired positioning of a respective conditioning surface (not shown) above the polishing platen 120, thereby allowing an efficient reworking of the corresponding pad surface in order to enhance uniformity of process conditions throughout the processing of a plurality of substrates. The polishing tool 100 further comprises a window 121 formed in the polishing platen 120 in which an optical transparent material may be provided to enable optical access of a surface to be treated during the operation of the polishing tool 100.
FIG. 1e schematically illustrates the polishing tool 100 in a schematic cross-sectional view, wherein an optical measurement system 140 is arranged below the window portion 121. The optical system 140 may be attached to a support member 141, which in turn may be mechanically coupled to a drive assembly 122 that is configured to rotate the polishing platen 120. The optical system 140 comprises a light source 142 configured to emit a light beam and to direct the same to the surface of the substrate 151 that is currently being processed. Moreover, the optical system 140 includes a detector 143 configured and arranged to receive a light beam reflected by the surface of the substrate 151. The respective light beams may be received through a substantially transparent material provided in the window portion 121, as previously explained. The light source 142 and the detector 143 are coupled to a CMP control unit 101, which is configured to evaluate the signal obtained from the detector 143 and, if required, to appropriately drive the light source 142. The control unit 101 is further configured to control the drive assembly 122 connected to the polishing platen 120 and also to control a drive assembly 123 connected to the polishing head 130. Furthermore, the control unit 101 may control movement of the pad conditioner 160.
During operation of the polishing tool 100, the substrate 151 may be loaded onto the polishing head 130 on the basis of well-known components, such as robot handlers and the like, wherein the polishing head 130 may itself be configured to provide the respective substrate handling and transport activities within the polishing tool 100. Furthermore, the substrate 151 loaded onto the polishing head 130 may be brought into a respective operating position and the corresponding relative motion between the polishing platen, i.e., a respective pad 124 attached thereto, and the polishing head 130 is established on the basis of the drive assemblies 122 and 123. Prior to and/or during the relative motion, an appropriate slurry substance (not shown) is supplied to the surface of the pad 124, wherein the slurry material may include a chemical agent or any other component for enhancing the overall removal rate or providing enhanced surface conditions during the corresponding polishing process. The pad conditioner 160 (see FIG. 1d) may be continuously or temporarily in contact with the corresponding polishing surface of the pad 124 in order to “rework” the respective surface structure. During operation of the polishing tool 100, the window portion 121 may pass the substrate surface, thereby providing an optical response to a light beam provided by the light source 142, which is received by the detector 143, which may provide a measurement signal to the control unit 101 indicating the reflectance of the surface portion illuminated by the light source 142. For example, when removing material of the metal layer 155 (see FIG. 1b), an initial reflectance of the layer 155 may be moderately high, due to the optical characteristics of the material of the layer 155 and due to a moderately pronounced overall surface topography obtained after the deposition of the layer 155, as previously explained. Upon removing material of the layer 155, the initial surface topography may be reduced, thereby enhancing the intensity of the reflected light beam, which may then remain substantially stable as long as the entire substrate surface is covered by the highly reflective material of the layer 155. In a final phase of the polishing process, surface portions of the substrate 151 may be increasingly cleared, thereby typically reducing the average reflectivity due to the different optical characteristics of the material 152 (FIGS. 1a-1c) compared to the material 155. Thus, the reduction in reflectance may be used as an indication of the status of the polishing process.
FIG. 1f schematically illustrates the time variation of a measurement signal obtained by the optical sensor system 140 of FIG. 1e during a final phase of the polishing process. As shown, the horizontal axis represents the polish time, while the vertical axis indicates the average reflectance, for instance the intensity of the reflected light beam received by the detector 143. Curve A represents the reflectance values over time, wherein, at a time interval t1, the reflectance begins to significantly decrease, thereby indicating that portions of the dielectric layer 152 are being exposed. Thus, during the time interval t2, a significant drop of the average reflectance may be observed, which may finally terminate into a tail portion of curve A corresponding to an interval t3 and having a significantly reduced slope, thereby indicating only minor changes in the optical surface characteristics of the layer 152 in combination with the residues of the metal layer 155. During the time interval t3, however, a significant degree of dishing and erosion, as indicated by 156, 157 in FIG. 1c, may occur while other device areas may still require further material removal to provide substantially electrically isolated metal features, as previously explained. Thus, within the time interval t3, an appropriate point of time te may be identified which may be considered as the end of the polishing process, thereby providing the desired electrical isolation of the metal feature, while attempting to not unduly over-polish the device 150. The definition of the endpoint of the polishing process may therefore have to “cover” the entire process window of the polishing process under consideration in order to substantially avoid undesired leakage currents caused by non-removed metal residues, while also maintaining device non-uniformities at a moderately low level, which may be caused by erosion and dishing effects. However, an appropriate definition of the endpoint, for instance in combination with appropriate process parameters at the final phase of the polishing process, may be difficult to be determined, in particular when the pattern density across the die regions have a wide distribution, as is, for instance, shown with respect to the wide trench 154 and the narrow lines and metal regions 156, 159 (FIGS. 1a-1c). Consequently, although optical endpoint detection provides enhanced process control, sophisticated device geometries may result in a less pronounced indication of clearance of the entire substrate, thereby possibly requiring additional over-polish times, which may lead to non-uniformities of metal lines with respect to resistivity and surface planarity.
The present disclosure is directed to various methods and systems that may avoid, or at least reduce, the effects of one or more of the problems identified above.